1. Technical Field
The invention relates to a means for enhancing signal margins when reading information from or writing information to dynamic random access memory (DRAM) cells, and more particularly to a circuit for providing a regulated boost voltage to drive selected local word lines.
2. Background Art
In a conventional DRAM array, the gate electrodes of the transfer devices are connected to a common word line, and the drains of the transfer devices are connected to a common bit line orthogonal to the word line. In reading or writing a selected cell, a word line is selected to turn on the appropriate transfer devices. The charge stored by the storage capacitor is then transferred to (or shared with) the bit line, which will experience a change in charge as a function of the charge stored by the cell and the capacitive coupling ratio between the cell and the bit line. Because this ratio is very low, the bit line voltage does not change by more than 100-200 millivolts or so. As is well known, a sense amplifier then amplifies this small voltage change.
Because of this small voltage difference, it is essential that the storage capacitor store a full rail potential (that is, a full "0" voltage level, typically ground potential, or a full "1" voltage level, typically 5 volts). If the transfer device is an NMOS, a full "1" level will not be stored; the capacitor will store a charge of VDD-Vt (where Vt is the threshold voltage of the device). Typically this problem has been addressed by the use of the so-called "bootstrapping" technique, in which the voltage on the gate or source of the transfer device is boosted to a threshold above Vdd. This enables the NMOS to pass a full VDD to the storage capacitor.
There are numerous references directed to the general idea of generating and applying a word line boost voltage as a clock signal to drive a word line. Of these, some rely on generating the boost voltage by use of a discrete capacitor within the word line driver (See U.S. Pat. No. 4,678,941 "Boost Word-Line Clock and Decoder-Driver Circuits in Semiconductor Memories" by Cao et al.; U.S. Pat. No. 4,639,622, "Boosting Word-Line Clock circuit for Semiconductor Memory," by Goodwin et al.; U.S. Pat. No. 4,814,647 "Fast Rise Time Boosting Circuit" by Tran; and U.S. Pat. No. 4,954,731 "Wordline Voltage Boosting Circuits for Complementary Dynamic RAMs" by Dhong et al.). Some others use a compensated supply to insure that the voltage on the boost capacitor stays relatively constant (see U.S. Pat. No. 4,896,297 "Circuit for Generating A Boosted Signal for a Word Line," by Miyatake et al.). In U.S. Pat. No. 4,649,523, "Semiconductor Memory with Boosted Word Line" by Holder, Jr., et al., a boost voltage is provided to the word lines at both the beginning and the end of the access cycle.
U.S. Pat. No. 5,038,325 "High Efficiency Charge Pump Circuit," by Douglas et al. discloses a boost circuit in which stray and decoupling capacitances are charged to the boost voltage by a charge pump, the output of which passes through a clamp network that maintains the boost voltage at the desired level. The boost circuitry is located in an area removed from the word lines, saving real estate in the memory arrays.
An article by R. Scheuerlien et al., entitled "Offset Word Line Architecture," 1987 Symposium On VLSI Circuits, Session VI-4, pg. 81-2, describes a word line drive system which utilizes a high-Vt PMOS as the pull down device for the driver. The array devices have a lower threshold than the support devices, such that they experience a high turnoff voltage to prevent leakage. The array word lines are boosted to one volt below ground. Reliance is placed on the high Vt of the driver device to turn the device off before it can experience high gate stresses. See also U.S. Pat. No. 4,905,314 for a teaching of the use of a high Vt device in a clocking circuit.
As device dimensions further decrease, FETs become more susceptible to failure due to high applied electric fields. At the same time, the boost techniques discussed above tend to establish high electric fields. Thus, a need exists for an efficient word line boost system that minimizes high electric fields.